FIG. 1A illustrates a conventional semiconductor wafer 100 comprising multiple die areas 102a, 102b, 102c and 102d. There may be many of these die areas on the wafer, although only four are shown here, for illustrative simplicity. The die areas (collectively referred to as “102”) are typically arranged in an array, or grid pattern, with rows and columns of substantially identical die areas covering the surface of the wafer 100, and each die area 102 is typically rectangular.
Dies 102a and 102b are in a horizontal (as viewed) row, and dies 102c and 102d are in another horizontal row. Dies 102a and 102c are in a vertical (as viewed) column, and dies 102b and 102d are in another vertical column.
A horizontal (as viewed) scribe area 104h is shown between the row of dies 102a and 102b, and the row of dies 102c and 102d. And, a vertical (as viewed) scribe area 104v is shown between the column of dies 102a and 102c, and the column of dies 102b and 102d. 
Horizontal and vertical saw paths 106h and 106v are shown within the scribe areas 104h and 104v, respectively. The scribe areas 104h and 104v may have a width “W” of approximately 100 μm (microns), and the saw paths 106h and 106v may have a width “w” of approximately 50 μm. Generally, the width of the saw path 106h or 106v corresponds to the width of a saw blade (not shown) plus tolerances (such as 5 μm) for alignment and placement. To singulate the die areas 102a-102d into separate dies (also called “dice”), the saw blade cuts through the wafer 100 along the saw paths 106h and 106v. 
This sawing of the wafer imposes mechanical stress on the wafer, which essentially comprises crystalline silicon. Due to these mechanical stresses, cracks can originate in the saw path (or in the scribe area), and propagate into the die areas, causing device failures.
As described in greater detail hereinbelow, cracking due to the saw blade cutting through the saw path may be inhibited from propagating to die area by structures (113 and 115) which serve as crack stop trenches.
FIG. 1B illustrates a portion of a wafer 101 (compare 100) prior to the formation of solder balls (or the formation of other die-to-package external conductive connection structures in other embodiments). A die area 105 of wafer 101 is a portion of wafer 101 from which a semiconductor die (not shown) is made. The wafer 101 typically includes multiple die areas 105 (compare die areas 102 in FIG. 1) separated by scribe areas (compare scribe areas 104h and 104v in FIG. 1).
FIG. 1B illustrates a portion of a scribe area 103 located adjacent to (to the left of, as viewed) the die area 105. A second die area (not shown) may be located to the left of scribe area 103. A semiconductor die fabricated in the die area 105 may, for example, be utilized in a flip chip configuration in a semiconductor package.
The wafer 101 includes an interconnect stack layer 107 located on top of a substrate 109. The stack layer 107 may include multiple layers of dielectric material and interconnecting electrical conductive structures such as vias and trench layers. These interconnecting electrically conductive structures are made of metal (e.g. copper, aluminum, silver, or gold) and electrically couple devices (not shown) formed in substrate 109 with external conductive connection structures such as e.g. solder balls. The multiple layers of interconnect stack layer 107 may be formed using single damascene processes or dual damascene process.
To singulate the die of a wafer, a saw blade (not shown) or other cutting device is used to separate the die areas (e.g. 105) from each other during the later stages of manufacture. A saw blade cuts the wafer at a saw path 111. Conductive structures 112 which are made of copper are located in saw path 111. These conductive structures may be utilized for testing and alignment guides during manufacture but typically are not electrically coupled to the devices formed in the substrate 109 of die area 105 and are not utilized during the operation of the die in its end use. During the singulation of the die, the copper of these conductive structures 112 in the saw path 111 may build up on the saw blade thereby causing problems during singulation.
The interconnect layer 107 comprises a passivation layer 121 which is formed of a dielectric passivation material such as silicon nitride. The passivation layer 121 is formed over the die areas e.g. 105 of wafer 101 and is utilized as a protective layer of the die area. Passivation layer 121 includes openings for coupling external conductive connection structures (e.g. solder balls) to electrically conductive pads (e.g. 131) in interconnect stack layer 107. A polyimide layer 124 is formed over die area 105 and may be utilized for stress relief and die protection. The polyimide layer 124 includes openings for coupling external conductive connection structures (e.g. solder balls) to electrically conductive pads (e.g. 131) in interconnect stack layer 107. A passivation layer 121 may be located over portions of the scribe area that do not include metals in the saw path that are to be removed.
An edge seal ring 119 and crack stop ring 117 extend around the perimeter of die area 105, in the interconnect stack layer 107. Theses structures are made of metal trenches with trench vias located in between the traces. Contact vias 120 of the seal ring 119 and crack stop ring 117 may be of a different material such as tungsten.
Conductive structures 113 and 115 are ring structures located on the edge of saw path 111 in stack layer 107 and surround die area 105. The saw blade may be 50 μm (microns) wide, and the scribe area may be 100 microns wide. And the structures 113 and 115 may be located 20 and 15 microns, respectively, from crack stop 117. The conductive structures 113 and 115 may be removed to form crack stop trenches in the interconnect stack layer 107.
Patents and Publications
US Patent Publication 20070243490, incorporated by reference herein, discloses prevention of plasma induced damage arising from etching of crack stop trenches in multi-layered low-k semiconductor devices. A method of fabricating a semiconductor device begins by forming a lower interconnection dielectric on a substrate and forming at least one active or passive device in the lower interconnection dielectric. An etch stop layer is formed on the lower interconnection dielectric and an interconnect stack layer is formed on the etch stop layer. At least one interconnect trench structure and at least one crack stop trench are etched in the interconnect stack layer while maintaining electrical isolation between the interconnect structure and the crack stop trench.
US Patent Publication 20060264035, incorporated by reference herein, discloses crack stop trenches in multi-layered low-k semiconductor devices. A method is provided for fabricating a semiconductor device. The method begins by forming on a substrate an interconnect stack layer that includes a plurality of layers with interconnecting metal overlying the substrate. After forming the interconnect stack layer, a crack stop trench is formed in the interconnect stack layer. Finally, the crack stop trench is filled with a prescribed material.
U.S. Pat. No. 6,951,801, incorporated by reference herein, discloses metal reduction in wafer scribe area. It further discloses a process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.
U.S. Pat. No. 6,261,945, incorporated by reference herein, discloses crackstop and oxygen barrier for low-K dielectric integrated circuits. A copper-interconnect, low-K dielectric integrated circuit has reduced corrosion of the interconnect when the crackstop next to the kerf is also used as the primary barrier to oxygen diffusion through the dielectric, with corresponding elements of the crackstop being constructed simultaneously with the circuit interconnect elements; e.g. horizontal interconnect elements have a corresponding structure in the crackstop and vias between interconnect layers have corresponding structures in the crackstop.